// Copyright (c) 2024 Zero ASIC Corporation
// This code is licensed under Apache License 2.0 (see LICENSE for details)

`include "switchboard.vh"

module testbench (
    `ifdef VERILATOR
        input clk
    `endif
);
    `ifndef VERILATOR
        `SB_CREATE_CLOCK(clk)
    `endif

    localparam integer DW=256;

    // SB RX port

    `SB_WIRES(from_out_to_rtl, DW);
    `QUEUE_TO_SB_SIM(from_out_to_rtl, DW, "from_out_to_rtl.q");

    // SB TX port

    `SB_WIRES(from_rtl_to_in_a, DW);
    `SB_TO_QUEUE_SIM(from_rtl_to_in_a, DW, "from_rtl_to_in_a.q");

    `SB_WIRES(from_rtl_to_in_b, DW);
    `SB_TO_QUEUE_SIM(from_rtl_to_in_b, DW, "from_rtl_to_in_b.q");

    // loopback with data modification (add "1" to data)

    logic [7:0] in_a;
    logic [7:0] in_b;
    assign in_a[7:0] = from_out_to_rtl_data[7:0] + 1;
    assign in_b[7:0] = from_out_to_rtl_data[7:0] + 2;
    assign from_rtl_to_in_a_data[7:0] = in_a[7:0];
    assign from_rtl_to_in_b_data[7:0] = in_b[7:0];

    // genvar i;
    // generate
    //     for (i=0; i<(DW/8); i=i+1) begin
    //         assign from_rtl_data[(i*8) +: 8] = to_rtl_data[(i*8) +: 8] + 8'd1;
    //     end
    // endgenerate
    // always @(posedge clk) begin
    //     $monitor("out = %d in_a = %d, in_b = %d\n", from_out_to_rtl_data, in_a, in_b);
    // end

    assign from_rtl_to_in_a_dest = from_out_to_rtl_dest;
    assign from_rtl_to_in_a_last = from_out_to_rtl_last;
    assign from_rtl_to_in_a_valid = from_out_to_rtl_valid;
    assign from_rtl_to_in_b_dest = from_out_to_rtl_dest;
    assign from_rtl_to_in_b_last = from_out_to_rtl_last;
    assign from_rtl_to_in_b_valid = from_out_to_rtl_valid;
    assign from_out_to_rtl_ready = from_rtl_to_in_a_ready;

    // end simulation after receiving a packet of all 1's

    // always @(posedge clk) begin
    //     if (to_rtl_valid && ((&to_rtl_data) == 1'b1)) begin
    //         $finish;
    //     end
    // end

    // Waveforms

    `SB_SETUP_PROBES

endmodule
